HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1084

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 30
5. If a normal frame is received, the pin retains its high-impedance state at the timing for
(b) Retransmission when the smart card interface is in transmit mode (T = 0)
Figure 30.9 shows retransmit operations when the smart card interface is in transmit mode. Step
(1) to step (4) of figure 30.9 correspond to the following operation
1. After completion of transmission of one frame, if an error signal is returned from the receive
2. In T = 0 mode, the TEND bit in SCSSR is not set for a frame when an error signal indicating
3. If no error signal is returned from the receive side, the ERS bit in SCSSR is not set.
4. If no error signal is returned from the receive side, it is assumed that transmission of one
Rev. 3.00 Jan. 18, 2008 Page 1022 of 1458
REJ09B0033-0300
RDRF
PER
transmission of error signals.
side, the ERS bit in SCSSR is set to 1. If the RIE bit in SCSCR is set to enable, an ERI request
is issued. The ERS bit in SCSSR should be cleared to 0 before the sampling timing for the next
parity bit.
an error is received.
frame, including retransmission, is completed, and the TEND bit in SCSSR is set to 1. At this
time, if the TIE bit in SCSCR is set to enable, a TEI interrupt request is issued.
Figure 30.8
Ds
SIM Card Module (SIM)
D0 D1 D2 D3 D4 D5 D6 D7 DP
nth transmit frame
Retransmission when Smart Card Interface is in Receive Mode
DE
(1)
(2)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 DP
Retransmit frame
(5)
(4)
(3)
(DE)
Ds
D0 D1 D2 D3 D4
(n+1)th transmit frame