HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 407

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5.4
The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation
to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 9.11 shows an example. A Th cycle and a Tf cycle are
added before and after an ordinary cycle, respectively. In these cycles, RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
CSn Assert Period Expansion
Read
Write
A25 to A0
WEn (BEn)
D31 to D0
D31 to D0
Figure 9.11
DACKn*
RD/WR
CKIO
CSn
Note: * The waveform for DACKn is when active low is specified.
RD
BS
Th
CSn Assert Period Expansion
T1
Rev. 3.00 Jan. 18, 2008 Page 345 of 1458
T2
Section 9
Tf
Bus State Controller (BSC)
REJ09B0033-0300