HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 502

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10
(b) Burst Mode
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed continuously
without releasing the bus mastership until the transfer end condition is satisfied. In external
request mode with level detection of the DREQ pin, however, when the DREQ pin is not active,
the bus mastership passes to the other bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Burst mode cannot be used for other than CMT (channels 0 to 4) when the on-chip peripheral
module is the transfer request source.
Figure 10.11 shows DMA transfer timing in burst mode.
Rev. 3.00 Jan. 18, 2008 Page 440 of 1458
REJ09B0033-0300
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 10.10 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
Bus cycle
Figure 10.10
DREQ
Direct Memory Access Controller (DMAC)
Bus cycle
DREQ
CPU
Figure 10.11
CPU
CPU
Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
(Dual Address, DREQ Low Level Detection)
CPU
CPU
CPU
DMA Transfer Example in Burst Mode
DMAC DMAC CPU
Read/Write
DMAC DMAC DMAC
Read
More than 16 or 64 Bφ
(change by the CPU, LCDC, and USBH states of using bus)
Write
Read
CPU DMAC DMAC CPU
DMAC DMAC
Write
Read/Write
Read
DMAC
Write
CPU