HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 787

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(5)
The SIOF can separately reset the transmit and receive units by setting the following bits to 1.
• Transmit reset: TXRST bit in SICTR
• Receive reset: RXRST bit in SICTR
Table 21.11 shows the details of initialization upon transmit or receive reset.
Table 21.11 Transmit and Receive Reset
Notes: Refer to the following procedure to operate the transmit reset/receive reset.
Type
Transmit reset
Receive reset
Transmit/Receive Reset
1 Set the master clock source in the peripheral clock. (Write 1 (master clock = Pφ
2 Set the prescaler count value of the baud rate generator to 1/1. (Write "00000" (division
3 Set the division ratio in the bit rate generator's output level to 1/1. (Write "111" (division
4 Reset transmit/receive operation. (To reset, write "1" to the TXRST or RXRST bit in the
(peripheral clock)) to the MSSEL bit in the SISCR register).
ratio = 1/1) to BRPS bits 4 to 0 in the SISCR register).
ratio =1/1) to BRDV bits 2 to 0 in the SISCR register).
SICTR register).
Objects Initialized
SITDR
Transmit FIFO write pointer and read pointer
TCRDY, TFEMP, and TDREQ bits in SISTR
TXE bit in SICTR
SIRDR
Receive FIFO write pointer and read pointer
RCRDY, RFFUL, and RDREQ bits in SISTR
RXE bit in SICTR
Rev. 3.00 Jan. 18, 2008 Page 725 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300