HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1490

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Jan. 18, 2008 Page 1428 of 1458
REJ09B0033-0300
Item
31.3.7 Response Registers 0 to
16 and D (RSPR0 to RSPR16 and
RSPRD)
31.3.14 Interrupt Status Registers
0 and 1 (INTSTR0 and INTSTR1)
31.3.15 Transfer Clock Control
Register (CLKON)
Page Revision (See Manual for Details)
1040
1051
1053 Changed
1053
Changed
Amended
The 33-MHz peripheral clock is needed, and bits
CSEL3 to CSEL0 should be set to 0001 for a 16.5-
Mbps transfer clock of the MMCIF.
Changed
Bit
7 to 5
4 to 0
Bit
2
Bit
7
Bit Name Description
CRCERI
Bit Name Description
CLKON
Bit Name

RSPRD
CRC Error Flag
[Setting condition]
When a CRC error for command response
or receive data, and CRC status error for
transmission data response are detected
while CRCERIE = 1.
For any non-R2 command response, CRC
is checked when the RTY4 in RSPTYR is
set for enabling.
For the R2 command response, CRC is
not checked; therefore, this flag is not set.
[Clearing condition]
Write 0 after reading CRCERI = 1.
Note:
Clock On
0: Stops the transfer clock output from the
1: Outputs the transfer clock from the
CLK/SCLK pin.
halt the command sequence by
setting the CMDOFF bit to 1.
CLK/SCLK pin.
Initial Value
All 0
All 0
When the CRC error occurs,
R/W

R/W