HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 237

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

4.2.2
The page table entry register low (PTEL) register residing at address H'FFFF FFF4, and used to
store the physical page number and page management information to be recorded in the TLB by
the LDTLB instruction. The contents of this register are only modified in response to a software
command.
4.2.3
The translation table base register (TTB) residing at address H'FFFF FFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB automatically.
TTB is available to software for general purposes. The initial value is undefined.
4.2.4
The MMU control register (MMUCR) residing at address H'FFFF FFE0. Any program that
modifies MMUCR should reside in the P1 or P2 area.
Bit
31 to 29
28 to 10
9
8
7
6, 5
4
3
2
1
0
Page Table Entry Register Low (PTEL)
Translation Table Base Register (TTB)
MMU Control Register (MMUCR)
Bit Name

PPN

V

PR
SZ
C
D
SH

Initial
Value
All 0

0

0





0
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
The Number of the Physical Page
Page Management Information
For more details, see section 4.3, TLB Functions.
Section 4 Memory Management Unit (MMU)
Rev. 3.00 Jan. 18, 2008 Page 175 of 1458
REJ09B0033-0300