HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 294

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
(2)
• Conditions
• Types
• Save address
• Exception code
• Remarks
(3)
• Conditions
When a hit access violates the TLB protection information (PR bits).
• Types
• Save address
• Exception code
• Remarks
Rev. 3.00 Jan. 18, 2008 Page 232 of 1458
REJ09B0033-0300
Comparison of TLB addresses shows address match but V = 0.
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'040
An exception occurred during write: H'060
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'0A0
An exception occurred during write: H'0C0
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
TLB invalid exception
TLB protection exception