HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 196

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operating Unit
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits
in DSR. The DC bit result is:
(1)
The DC bit is always cleared.
(2)
Bit 31 of the operation result is loaded into the DC bit.
(3)
The DC bit is set when the operation result is zero; otherwise it is cleared.
(4)
The DC bit is always cleared.
(5)
The DC bit is always cleared.
(6)
The DC bit is always cleared.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
Rev. 3.00 Jan. 18, 2008 Page 134 of 1458
REJ09B0033-0300
Carry or Borrow Mode: CS[2:0] = 000
Negative Value Mode: CS[2:0] = 001
Zero Value Mode: CS[2:0] = 010
Overflow Mode: CS[2:0] = 011
Signed Greater Than Mode: CS[2:0] = 100
Signed Greater Than or Equal Mode: CS[2:0] = 101