HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 729

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 20.11 and 20.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and the CKS4 to CKS0 bits in
2. When the slave address matches in the first frame following detection of the start condition,
(Master output)
(Master output)
(Slave output)
(Slave output)
processing
ICCKS1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
ICDRS
ICDRR
ICDRT
TDRE
TEND
SCL
SDA
SDA
SCL
User
TRS
Slave Receive Operation
Figure 20.10
A
9
Bit 7
1
Bit 6
2
Slave Transmit Mode Operation Timing (2)
Bit 5
3
Data n
Bit 4
[3] Clear TEND
4
Bit 3
5
Bit 2
6
Rev. 3.00 Jan. 18, 2008 Page 667 of 1458
[4] Read ICDRR (dummy read)
Bit 1
Slave transmit mode
after clearing TRS
7
Bit 0
Section 20
8
9
A
I
2
C Bus Interface (IIC)
REJ09B0033-0300
[5] Clear TDRE
Slave receive
mode