HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 48

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 35 I/O Ports
Figure 35.1 Port A .................................................................................................................... 1179
Figure 35.2 Port B .................................................................................................................... 1181
Figure 35.3 Port C .................................................................................................................... 1183
Figure 35.4 Port D .................................................................................................................... 1185
Figure 35.5 Port E..................................................................................................................... 1187
Figure 35.6 Port F..................................................................................................................... 1190
Figure 35.7 Port G .................................................................................................................... 1193
Figure 35.8 Port H .................................................................................................................... 1195
Figure 35.9 Port J ..................................................................................................................... 1197
Figure 35.10 Port K .................................................................................................................. 1199
Figure 35.11 Port L................................................................................................................... 1201
Figure 35.12 Port M.................................................................................................................. 1203
Figure 35.13 Port P................................................................................................................... 1205
Figure 35.14 Port R .................................................................................................................. 1207
Figure 35.15 Port S................................................................................................................... 1209
Figure 35.16 Port T................................................................................................................... 1211
Figure 35.17 Port U .................................................................................................................. 1213
Figure 35.18 Port V .................................................................................................................. 1215
Section 36 User Debugging Interface (H-UDI)
Figure 36.1 Block Diagram of H-UDI...................................................................................... 1218
Figure 36.2 TAP Controller State Transitions .......................................................................... 1231
Figure 36.3 H-UDI Data Transfer Timing................................................................................ 1233
Figure 36.4 H-UDI Reset.......................................................................................................... 1233
Section 38 Electrical Characteristics
Figure 38.1 EXTAL Clock Input Timing ................................................................................. 1316
Figure 38.2 CKIO Clock Output Timing.................................................................................. 1316
Figure 38.3 CKIO Clock Input Timing .................................................................................... 1316
Figure 38.4 Power-On Oscillation Settling Time ..................................................................... 1317
Figure 38.5 Oscillation Settling Time on Return from Standby (Return by Reset).................. 1317
Figure 38.6 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ)....... 1317
Figure 38.7 PLL Synchronization Settling Time by Reset, NMI or IRQ Interrupts................. 1318
Figure 38.8 Reset Input Timing................................................................................................ 1320
Figure 38.9 Interrupt Signal Input Timing................................................................................ 1320
Figure 38.10 Bus Release Timing ............................................................................................ 1321
Figure 38.11 Pin Drive Timing at Standby............................................................................... 1321
Figure 38.12 Basic Bus Cycle in Normal Space (No Wait)...................................................... 1324
Figure 38.13 Basic Bus Cycle in Normal Space (Software Wait 1) ......................................... 1325
Rev. 3.00 Jan. 18, 2008 Page xlviii of lxii