HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 312

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8
8.3.3
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to
IRQ0 individually: rising edge, falling edge, high level, or low level.
Rev. 3.00 Jan. 18, 2008 Page 250 of 1458
REJ09B0033-0300
Bit
15
14
13
12
Bit Name
MAI
IRQLVL
BLMSK
—
Interrupt Control Register 1 (ICR1)
Interrupt Controller (INTC)
Initial
Value
0
1
0
0
R/W
R/W
R/W
R/W
R
Description
All Interrupt Mask
When this bit is set to 1, all interrupt requests are masked
while low level is input to the NMI pin. The NMI interrupt
is masked in standby mode.
0: When the NMI pin is low, all interrupt requests are not
1: When the NMI pin is low, all interrupt requests are
Interrupt Request Level Detection
Enables or disables the use of pins IRQ3 to IRQ0 as four
independent interrupt pins. The IRQ4 and IRQ5 are not
affected.
0: Use of pins IRQ3 to IRQ0 as four independent interrupt
1: Use of pins IRL3 to IRL0 as encoded 15 level interrupt
BL Bit Mask
When the BL bit in the SR register is set to 1, specifies
whether the NMI interrupt is masked.
0: When the BL bit is set to 1, the NMI interrupt is masked
1: The NMI interrupt is accepted regardless of the BL bit
Reserved
This bit is always read as 0. The write value should
always be 0.
masked
masked
pins enabled
pins
setting