HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 262

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Cache
5.2.1
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which
invalidates all cache entries), and WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of the CCR1 register should be placed in
address space that is not cached.
Rev. 3.00 Jan. 18, 2008 Page 200 of 1458
REJ09B0033-0300
Bit
31 to 4 
3
2
1
0
Bit Name
CF
CB
WT
CE
Cache Control Register 1 (CCR1)
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Cache Flush
Writing 1 flushes all cache entries (clears the V, U, and
LRU bits of all cache entries to 0). This bit is always
read as 0. Write-back to external memory is not
performed when the cache is flushed.
Write-Back
Indicates the cache’s operating mode for space P1.
0: Write-through mode
1: Write-back mode
Write-Through
Indicates the cache’s operating mode for spaces P0,
U0, and P3.
0: Write-back mode
1: Write-through mode
Cache Enable
Indicates whether the cache function is used.
0: The cache function is not used.
1: The cache function is used.