HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 446

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 9
• Deep power-down mode
If the RMODE bit of the SDCR is set to 1 while the DEEP and RFSH bits of the SDCR are set to
1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0,
the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access
after returning from the deep power-down mode, the power-up sequence must be re-executed.
Rev. 3.00 Jan. 18, 2008 Page 384 of 1458
REJ09B0033-0300
A12/A11*
The low-power SDRAM supports the deep power-down mode as a low-power consumption
mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the
deep power-down mode, self-refresh will not be performed on any memory area. This mode is
effective in systems where all of the system memory areas are used as work areas.
D31 to D0
A25 to A0
DACKn*
DQMxx
RD/WR
BA1*
BA0*
CKIO
CSn
RAS
CAS
BS
3
1
2
4
Notes:
Bus State Controller (BSC)
1. Address pin to be connected to the BA1 pin of SDRAM.
2. Address pin to be connected to the BA0 pin of SDRAM.
3. Address pin to be connected to the A10 pin of SDRAM.
4. The waveform for DACKn is when active low is specified.
PALL
Tp
Tpw
Figure 9.29
REF
Trr
Trc
EMRS Command Issue Timing
Trc
Hi-Z
REF
Trr
Trc
Trc
Tmw
MRS
Tnop
Temw
EMRS
Tnop

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