HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1194

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 33 User Break Controller (UBC)
4. When data access (address + data) is specified as a break condition:
33.3.7
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt
2. The values stored in BRSR and BRDR are as given below due to the kind of branch.
3. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
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When a data value is added to the break conditions, the address of an instruction that is within
two instructions of the instruction that matched the break condition is saved in the SPC. At
which instruction the break occurs cannot be determined accurately.
When a delay slot instruction matches the condition, the branch destination address is saved in
the SPC. If the instruction following the instruction that matches the break condition is a
branch instruction, the break may occur after the branch instruction or delay slot has finished.
In this case, the branch destination address is saved in the SPC.
exception) is generated, the branch source address and branch destination address are stored in
BRSR and BRDR, respectively.
 If a branch occurs due to a branch instruction, the address of the branch instruction is saved
 If a branch occurs due to an interrupt or exception, the value saved in SPC due to exception
When a repeat loop of the DSP extended function is used, control being transferred from the
repeat end instruction to the repeat start instruction is not recognized as a branch, and the
values are not stored in BRSR and BRDR.
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the
PCTE bit (in BRCR) off and on, the values in the queues are invalid.
in BRSR and the address of the branch destination instruction is saved in BRDR.
occurrence is saved in BRSR and the start address of the exception handling routine is
saved in BRDR.
PC Trace