HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 379

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
11
10
9
8
7
6, 5
4
3
Bit Name
TRCD1
TRCD0

A3CL1
A3CL0

TRWL1
TRWL0
Initial
Value
0
1
0
1
0
All 0
0
0
R/W
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Description
Number of Cycles from ACTV Command to
READ(A)/WRIT(A) Command
Specify the number of minimum cycles from issuing ACTV
command to issuing READ(A)/WRIT(A) command. The
setting for areas 2 and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
This bit is always read as 0. The write value should always
be 0.
CAS Latency for Area 3.
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
When connecting the SDRAM to area 2 and area 3, set
the CAS latency to the bits 8 and 7 in the CS2WCR
register and the SDMR2 and SDMR3 registers for SDRAM
mode setting. (See table 9.19.)
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Cycles from WRITA/WRIT Command to Auto-
Precharge/PRE Command
Specifies the number of cycles from issuing WRITA/WRIT
command to the start of auto-precharge or to issuing PRE
command. The setting for areas 2 and 3 is common.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 3.00 Jan. 18, 2008 Page 317 of 1458
Section 9
Bus State Controller (BSC)
REJ09B0033-0300