HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1058

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 30
Rev. 3.00 Jan. 18, 2008 Page 996 of 1458
REJ09B0033-0300
Bit
6
Bit Name
RDRF
SIM Card Module (SIM)
Initial
Value
0
R/W
R/W
Description
Receive Data Register Full
Indicates that received data is stored in the receive data
register (SCRDR).
0: Indicates that no valid received data is stored in SCRDR
[Clearing conditions]
1: Indicates that valid received data is stored in SCRDR
[Setting condition]
When serial reception is completed normally, and received
data is transferred from SCRSR to SCRDR.
Note: In T = 0 mode, when a parity error is detected during
On reset
When data is read from SCRDR
When 0 is written to RDRF
reception, the SCRDR contents and RDRF flag are
unaffected, and the previous state is retained.
On the other hand, in T = 1 mode, when a parity
error is detected during reception, the received data
is transferred to SCRDR, and the RDRF flag is set to
1.
In both T = 0 and T = 1 modes, even if the RE bit in
the serial control register (SCSCR) is cleared to 0,
the SCRDR contents and RDRF flag are unaffected,
and the previous state is retained.

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