HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1065

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

30.3.10 Serial Control 2 Register (SCSC2R)
SCSC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt
(RXI) requests.
Bit
2
1
0
Bit
7
6 to 0 
Bit Name
SINV
RST
SMIF
Bit Name
EIO
Initial
Value
0
0
1
Initial
Value
0
All 0
R/W Description
R/W Smart Card Data Inversion
R/W Smart Card Reset
R/W Smart Card Interface Mode Select
R/W Description
R/W Error Interrupt Only
R
Specifies inversion of the data logic level. In combination with
the function of bit 3, used for transmission to or reception from
the inverse convention card. The SINV bit does not affect the
parity bit.
0: Transmits the SCTDR contents without change.
1: Inverts the SCTDR contents and transmits it.
Controls the output of the SIM_RST pin of the smart card
interface.
0: The SIM_RST pin of the smart card interface outputs low
1: The SIM_RST pin of the smart card interface outputs high
This bit is always read as 1. The write value should always be 1.
When the EIO bit is 1, even if the RIE bit is set to 1, a receive
data full interrupt (RXI) request is not sent to the CPU. When the
DMAC is used with this setting, the CPU processes only ERI
requests.
Receive data full interrupt (RXI) requests are determined by the
RIE bit setting.
Reserved
These bits are always read as 0. The write value should always
be 0.
Stores received data in SCRDR without change.
Inverts received data and stores it in SCRDR.
level.
level.
Rev. 3.00 Jan. 18, 2008 Page 1003 of 1458
Section 30
SIM Card Module (SIM)
REJ09B0033-0300