HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1107

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

31.3.12 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Bit
7
6
5
4
Bit Name
BUSY
FIFO_
FULL
FIFO_
EMPTY
CWRE
Initial
Value
0
0
0
0
R
R
R
R/W
R
FIFO Full
When read data is received, this bit is set to 1 after FIFO has
been full. This bit is cleared to 0 when RD_CONTI is set to 1
or command sequence is ended.
0: The FIFO is empty
1: The FIFO is full
FIFO Empty
When write data is transmitted, this bit is set to 1 after FIFO
has been empty. This bit is cleared to 0 when DATAEN is
set to 1 or command sequence is ended.
0: The FIFO includes data
1: The FIFO is empty
Command Register Write Enable
Indicates whether the CMDR command is being transmitted
or has been transmitted.
0: The CMDR command has been transmitted, or the
1: The CMDR command is waiting for transmission or is
Description
Command Busy
Indicates command execution state. When the CMDOFF bit
in OPCR is set to 1, this bit is cleared to 0 because the
MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state
1: Command sequence execution in progress
START bit in CMDSTRT has not been set yet, so the new
command can be written.
being transmitted. If the new command is written, a
malfunction will result.
Section 31
Rev. 3.00 Jan. 18, 2008 Page 1045 of 1458
MultiMediaCard Interface (MMCIF)
REJ09B0033-0300