HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 567

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3
Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register
(TCOR). TCNT counts down. The auto-reload function enables synchronized counting.
14.3.1
When the STR0 to STR2 bits in the timer start register (TSTR) are set to 1, the corresponding
timer counter (TCNT) starts counting. When TCNT underflows, the UNF flag in the
corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an
interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT
and the down-count operation is continued.
(1)
An example of the procedure for setting the count operation is shown in figure 14.2.
Count Operation Setting Procedure
Note:
Operation
Counter Operation
When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Set interrupt generation
Set timer constant
Select operation
Select counter
Initialize timer
Start counting
register
counter
clock
Figure 14.2 Setting Count Operation
(1)
(2)
(3)
(4)
(5)
(1) Select the counter clock with the
(2) Use the UNIE bit in TCR to set
(3) Set a value in the timer constant
(4) Set the initial value in the timer
(5) Set the STR bit in the timer start
bits TPSC2 to TPSC0 in the
timer control register (TCR).
whether to generate an interrupt
when TCNT underflows.
register (TCOR) (the cycle is the
set value plus 1).
counter (TCNT).
register (TSTR) to 1 to start
counting.
Rev. 3.00 Jan. 18, 2008 Page 505 of 1458
Section 14 Timer Unit (TMU)
REJ09B0033-0300