HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 514

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10
10.5.3
1. Before making a transition to standby mode, either wait until DMA transfer finishes or
2. If an on-chip peripheral module whose clock supply is to be stopped by the module standby
3. Do not write to SAR, DAR, DMATCR, or DMARS during DMA transfer.
Concerning Above Notes 1 and 2:
DMA transfer end can be confirmed by checking whether the TE bit in CHCR is set to 1.
To suspend DMA transfer, clear the DE bit in CHCR to 0.
Rev. 3.00 Jan. 18, 2008 Page 452 of 1458
REJ09B0033-0300
(high active)
(active-high)
Figure 10.22
(overrun 0,
(overrun 1,
high level)
high level)
Bus cycle
Bus cycle
suspend DMA transfer.
function is performing DMA transfer, either wait until DMA transfer finishes or suspend DMA
transfer before making a transition to module standby mode.
DREQ
DREQ
DACK
DACK
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles and So DREQ
CKIO
CKIO
Other Notes
Direct Memory Access Controller (DMAC)
First acceptance Second acceptance
CPU
CPU
First acceptance
Dead zone
Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Acceptance started
Sampling is Accepted Normally)
DMAC write or read
DMAC write or read
Dead zone
Dead zone
Second acceptance
Dead zone
Acceptance
started
Third acceptance
Third acceptance
Dead zone
Dead zone
Acceptance
started
Acceptance started