HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 425

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(4)
A read access ends in one cycle when data exists in non-cacheable region and the data bus width is
larger than or equal to access size. As the burst length is set to 1 in SDRAM burst read/single
write mode, only the required data is output. Consequently, no unnecessary bus cycles are
generated even when a cache-through area is accessed.
Figure 9.16 shows the single read basic timing.
Single Read
Figure 9.16
A12/A11*
D31 to D0
A25 to A0
DACKn*
Notes:
RD/WR
DQMxx
CKIO
RAS
CAS
CSn
BS
1
2
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Basic Timing for Single Read (Auto-Precharge)
Tr
Tc1
Td1
Rev. 3.00 Jan. 18, 2008 Page 363 of 1458
Tde
Section 9
Tap
Bus State Controller (BSC)
REJ09B0033-0300