HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 565

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
14.2.2
TCR are 16-bit readable/writable registers that control the timer counters (TCNT) and interrupts.
TCR control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow
has been set to 1, and also carry out counter clock selection.
TCR are initialized to H'0000 at a power-on reset or manual reset. They are retained in standby or
sleep mode.
Bit
15 to 9 —
8
7, 6
5
Bit Name
UNF
UNIE
Timer Control Registers (TCR)
Initial
Value
All 0
0
All 0
0
R/W
R
R/(W)* Underflow Flag
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Status flag that indicates occurrence of a TCNT
underflow.
0: TCNT has not underflowed
[Clearing condition]
0 is written to UNF
1: TCNT has underflowed
[Setting condition]
TCNT underflows
Reserved
These bits are always read as 0. The write value should
always be 0.
Underflow Interrupt Control
Controls enabling of interrupt generation when the status
flag (UNF) indicating TCNT underflow has been set to 1.
0: Interrupt due to UNF (TUNI) is disabled
1: Interrupt due to UNF (TUNI) is enabled
Rev. 3.00 Jan. 18, 2008 Page 503 of 1458
Section 14 Timer Unit (TMU)
REJ09B0033-0300

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