HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1185

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
6
5, 4
3
2, 1
0
Bit Name
PCBB

SEQ

ETBE
Initial
Value
0
All 0
0
All 0
0
R/W
R/W
R
R/W
R
R/W
Description
PC Break Select B
Selects the break timing of the instruction fetch cycle
for channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
1: PC break of channel B is set after instruction
Reserved
These bits are always read as 0. The write value
should always be 0.
Sequence Condition Select
Selects two conditions of channels A and B as
independent or sequential conditions.
0: Channels A and B are compared under
1: Channels A and B are compared under sequential
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Execution Times Break Enable
Enables the execution-times break condition only on
channel B. If this bit is 1 (break enable), a user break
is issued when the number of break conditions
matches with the number of execution times that is
specified by BETR.
0: The execution-times break condition is disabled on
1: The execution-times break condition is enabled on
execution
execution
independent conditions
conditions (channel A, then channel B)
channel B
channel B
Rev. 3.00 Jan. 18, 2008 Page 1123 of 1458
Section 33 User Break Controller (UBC)
REJ09B0033-0300