HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 290

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
• Save address
• Exception code
• Remarks
(2)
• Conditions
Note: For details on undefined code, refer to table 2.12. When an undefined code other than
• Types
• Save address
• Exception code
• Remarks
Rev. 3.00 Jan. 18, 2008 Page 228 of 1458
REJ09B0033-0300
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H'0E0
An exception occurred during write: H'100
The virtual address (32 bits) that caused the exception is set in TEA.
 When undefined code not in a delay slot is decoded
 When a privileged instruction not in a delay slot is decoded in user mode
Instruction synchronous, re-execution type
An instruction address where an exception occurs
H'180
None
Illegal general instruction exception
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
H'F000 to H'FFFF is decoded, operation cannot be guaranteed.