HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 506

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10
10.4.5
(1)
When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
(2)
Figures 10.13, 10.14, 10.15, and 10.16 show the sample timing of the DREQ input in each bus
mode, respectively.
Rev. 3.00 Jan. 18, 2008 Page 444 of 1458
REJ09B0033-0300
Figure 10.13
Number of Bus Cycle States
DREQ Pin Sampling Timing
Number of Bus Cycle States and DREQ Pin Sampling Timing
Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
1st acceptance
CPU
Non-sensitive period
CPU
DMAC
Acceptance started
2nd acceptance
CPU