HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 939

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

26.3.7
LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image
recognized by the graphics driver. This register specifies how many bytes the address from which
data is to be read should be moved when the Y coordinates have been incremented by 1. This
register does not have to be equal to the horizontal width of the LCD panel. When the memory
address of a point (X, Y) in the two-dimensional image is calculated by Ax + By+ C, this register
becomes equal to B in this equation.
Bit
15 to 10 LAO15 to
9
8
7
6 to 0
LCDC Line Address Offset Register for Display Data Fetch (LDLAOR)
Bit Name Initial Value
LAO10
LAO9
LAO8
LAO7
LAO6 to
LAO0
All 0
1
0
1
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Line Address Offset
The minimum alignment unit of LDLAOR is 16 bytes.
Because the LCDC handles these values as 16-byte
data, the values written to the lower four bits of the
register are always treated as 0. The lower four bits of
the register are always read as 0. The initial values (×
resolution = 640) will continuously and accurately
place the VGA (640 × 480 dots) display data without
skipping an address between lines. For details, see
tables 26.3 and 26.4.
A binary exponential at least as large as the horizontal
width of the image is recommended for the LDLAOR
value while taking into consideration the software
operation speed. When the hardware rotation function
is used, the LDLAOR value should be a binary
exponential (in this example, 256) at least as large as
the horizontal width of the image (after rotation, it
becomes 240 in a 240 × 320 panel) instead of the
horizontal width of the LCD panel (320 in a 320 × 240
panel).
Rev. 3.00 Jan. 18, 2008 Page 877 of 1458
Section 26
LCD Controller (LCDC)
REJ09B0033-0300