HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1103

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

31.3.9
OPCR controls command operation abort, and suspends or continues data transfer.
Bit
7 to 1
0
Bit
7
6
5
Bit Name
—
START
Bit Name
CMDOFF 0
—
RD_
CONTI
Operation Control Register (OPCR)
Initial
Value
0
0
Initial
Value
All 0
0
R/W
R
R/W
R/W
R/W

R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Starts command transmission when 1 is written. This bit is
cleared by hardware.
Read Continue
Description
Command Off
Aborts all command operations (MMCIF command sequence)
when 1 is written after a command is transmitted. This bit is
then cleared by hardware.
Write enable period: from command transmission completion
to command sequence end
Writes 0: Operation is not affected.
Writes 1: Command sequence is forcibly aborted.
Reserved
This bit is always read as 0. The write value should always be
0.
After 1 is written, this bit is cleared by hardware when MMCIF
resumes reading data. Resumes read data reception when the
sequence is halted according to FIFO full or termination of
block reading in multiblock read.
Write enable period: while MCCLK for read data reception is
halted
Writes 0: Operation is not affected.
Writes 1: Resumes MCCLK output and read data reception.
Section 31
Rev. 3.00 Jan. 18, 2008 Page 1041 of 1458
MultiMediaCard Interface (MMCIF)
REJ09B0033-0300