HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 106

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
Rev. 3.00 Jan. 18, 2008 Page 44 of 1458
REJ09B0033-0300
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
2. Bank register
3. Bank register
4. Bank register
CPU
and indexed GBR indirect addressing mode.
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
31
(a) User mode register
Figure 2.3
configuration
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
R8
R9
SR
PR
PC
*1,*2
*2
*2
*2
*2
*2
*2
*2
Register Configuration in Each Processing Mode
0
31
(b) Privileged mode register
configuration (RB = 1)
R0_BANK1
R0_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1,*3
*1,*4
*3
*3
*3
*3
*3
*3
*3
*4
*4
*4
*4
*4
*4
*4
0
31
(c) Privileged mode register
configuration (RB = 0)
R0_BANK0
R0_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1,*4
*1,*3
*4
*4
*4
*4
*4
*4
*4
*3
*3
*3
*3
*3
*3
*3
0