HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 956

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 26
Note:
Rev. 3.00 Jan. 18, 2008 Page 894 of 1458
REJ09B0033-0300
Bit
7 to 1
0
Interrupt processing flow:
1. Interrupt signal is input
2. LDINTR is read
3. If MINTS, FINTS, VSINTS, or VEINTS is 1, a generated interrupt is memory access
4. If MINTS, FINTS, VSINTS, or VEINTS is 0, a generated interrupt is not memory access
5. UINTS is read.
6. If UINTS is 1, a generated interrupt is a user specified interrupt. Process for user
7. If UINTS is 0, a generated interrupt is not a user specified interrupt. Other processing is
Bit Name

UINTS
interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge
interrupt. Processing for each interrupt is performed.
interrupt, flame end interrupt, Vsync rising edge interrupt, or Vsync falling edge
interrupt.
specified interrupt is carried out.
performed.
LCD Controller (LCDC)
Initial Value
All 0
0
R/W
R
R/W
Description
Reserved.
These bits are always read as 0. The write value
should always be 0.
User Specified Interrupt State
This bit is set to 1 at the time an LCDC user
specified interrupt is generated (set state). During
the user specified interrupt handling routine, this
bit should be cleared by writing 0 to it.
0: LCDC did not generate a user specified
1: LCDC has generated a user specified interrupt
interrupt or has been informed that the
generated user specified interrupt has
completed
and has not yet been notified that the
generated user specified interrupt has
completed