HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 259

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1
• Capacity: 16 or 32 kbytes
• Structure: Instructions/data mixed, 4-way set associative
• Locking: Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode
• Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
• Replacement method: Least-recently used (LRU) algorithm
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
5.1.1
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section. Note
that the following sections will be described for the 16-kbyte mode as an example. For other cache
size modes, change the number of entries and size/way according to table 5.1. Each of the address
and data sections is divided into 256 entries. The entry data is called a line. Each line consists of
16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries) in the cache
as a whole (4 ways). The cache capacity is 16 kbytes as a whole.
Table 5.1
CACH001A_000020020800
Cache Size
16 kbytes
32 kbytes
Group 1 (P0, P3, and U0 areas)
Group 2 (P1 area)
Features
Cache Structure
Number of Entries and Size/Way in Each Cache Size
Number of Entries
256
512
Section 5 Cache
Rev. 3.00 Jan. 18, 2008 Page 197 of 1458
Size/Way
4 kbytes
8 kbytes
REJ09B0033-0300
Section 5 Cache