HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 54

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 3.16
Table 3.17
Table 3.18
Table 3.19
Table 3.20
Table 3.21
Table 3.22
Table 3.23
Table 3.24
Table 3.25
Table 3.26
Table 3.27
Table 3.28
Table 3.29
Table 3.30
Table 3.31
Table 3.32
Table 3.33
Table 3.34
Table 3.35
Table 3.36
Table 3.37
Table 3.38
Table 3.39
Table 3.40
Section 4 Memory Management Unit (MMU)
Table 4.1
Section 5 Cache
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Rev. 3.00 Jan. 18, 2008 Page liv of lxii
DSR Register Bits................................................................................................. 116
DSP Operation Instruction Formats...................................................................... 118
Correspondence between DSP Instruction Operands and Registers ..................... 119
DC Bit Update Definitions ................................................................................... 120
Examples of NOPX and NOPY Instruction Codes............................................... 122
Variation of ALU Fixed-Point Operations............................................................ 126
Correspondence between Operands and Registers ............................................... 126
Variation of ALU Integer Operations ................................................................... 131
Variation of ALU Logical Operations .................................................................. 133
Variation of Fixed-Point Multiply Operation ....................................................... 135
Correspondence between Operands and Registers ............................................... 136
Variation of Shift Operations................................................................................ 137
Operation Definition of PDMSB .......................................................................... 143
Variation of PDMSB Operation............................................................................ 144
Variation of Rounding Operation ......................................................................... 145
Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 146
Definition of Overflow Protection for Integer Arithmetic Operations.................. 146
Variation of Local Data Move Operations............................................................ 147
Correspondence between Operands and Registers ............................................... 148
DSP Mode Extended System Control Instructions ............................................... 149
Double Data Transfer Instruction ......................................................................... 151
Single Data Transfer Instructions ......................................................................... 152
Correspondence between DSP Data Transfer Operands and Registers ................ 153
DSP Operation Instructions .................................................................................. 154
Operation Code Map............................................................................................. 160
Access States Designated by D, C, and PR Bits ................................................... 183
Number of Entries and Size/Way in Each Cache Size.......................................... 197
LRU and Way Replacement (when Cache Locking Mechanism is Disabled)...... 199
Way Replacement when a PREF Instruction Misses the Cache ........................... 203
Way Replacement when Instructions other than the PREF Instruction
Miss the Cache...................................................................................................... 203
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)................ 203
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)................ 204
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)................ 204
Address Format Based on the Size of Cache to be Assigned to Memory............. 211