HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 658

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18
Rev. 3.00 Jan. 18, 2008 Page 596 of 1458
REJ09B0033-0300
Bit
10
9
8
Bit Name
ERIE
BRIE
DRIE
Serial Communication Interface with FIFO (SCIF)
Initial Value R/W
0
0
0
R/W
R/W
R/W
Break Interrupt Enable
Description
Receive Error Interrupt Enable
Enables or disables the generation of a receive-error
(framing error/parity error) interrupt requested when
the ER flag in SCSSR is set to 1.
0: The receive-error interrupt disabled*
1: The receive-error interrupt enabled
Note:
Enables or disables the generation of break-receive
interrupt requested when the BRK flag in SCSSR is
set to 1.
0: The break-receive interrupt disabled*
1: The break receive interrupt enabled
Note:
Receive Data Ready Interrupt Enable
Disables or enables the generation of receive-data-
ready interrupt when the DR flag in SCSSR is set to 1.
0: The receive-data-ready interrupt disabled
1: The receive-data-ready interrupt enabled
Note:
*
*
*
The receive-error interrupt request is
cleared by reading the ER flag after it has
been set to 1, then clearing the flag to 0,
or clearing the ERIE bit to 0.
The break-receive interrupt request is
cleared by reading the BRK flag after it
has been set to 1, then clearing the flag to
0, or clearing the BRIE bit to 0.
The receive-data-ready interrupt request is
cleared by reading the DR flag after it has
been set to 1, then clearing the flag to 0,
or clearing the DRIE bit to 0.