HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1470

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 3.00 Jan. 18, 2008 Page 1408 of 1458
REJ09B0033-0300
Item
Section 11 Clock Pulse Generator
(CPG)
11.1 Features
Table 11.1 Pin Configuration
11.3 Clock Operating Modes
Section 11 Clock Pulse Generator
(CPG)
11.4.1 Frequency Control
Register (FRQCR)
457
458
Page Revision (See Manual for Details)
453
461
461
Changed
Deleted
• Clocks for specific modules generated: In addition to
Amended
Note: To prevent device malfunction, the value of the
Mode 0: …… The frequency of CKIO ranges from
Changed
…FRQCR is initialized by a power-on reset, but not
initialized by a power-on reset at the WDT overflow.
FRQCR retains its value in a manual reset and in
standby mode.
Deleted
Bit
15
Iφ, Pφ, and Bφ, two other clocks, USBH/USBF clock
(Uφ), can be generated for specific modules. Uφ is a
clock input from an external pin.
Bit Name Description
PLL2EN
mode control pin is sampled only upon a power-
on reset.
24.00 to 66.67 MHz, because the input clock
frequency ranges from 24.00 to 66.67 MHz.
PLL2 Enable
PLL2EN specifies whether make the PLL
circuit 2 ON in clock operating mode 7.
When the PLL circuit 2 is necessary to
output the USBH/USBF clock, PLL2EN
makes the circuit ON. The PLL circuit 2 is
ON in non-clock operating mode 7
regardless of the PLL2EN setting.
0: PLL circuit 2 is OFF
1: PLL circuit 2 is ON