HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 886

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
25.3.25 EP1 Receive Data Size Register (EPSZ1)
EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received
from the host. FIFO of endpoint 1 has a dual-buffer configuration. The size of the received data
indicated by this register is the size of the currently selected side (can be read by CPU).
25.3.26 EP4 Receive Data Size Register (EPSZ4)
EPSZ4 is a receive data size resister for endpoint 4. EPSZ4 indicates the number of bytes received
from the host. FIFO of endpoint 4 has a dual-buffer configuration. The size of the received data
indicated by this register is the size of the currently selected side (can be read by CPU).
25.3.27 Trigger Register (TRG)
TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2, and
EP3. The packet enable trigger for the IN FIFO register and read complete trigger for the OUT
FIFO register are triggers to be given.
Rev. 3.00 Jan. 18, 2008 Page 824 of 1458
REJ09B0033-0300
Bit
7 to 0 
Bit
7 to 0 
Bit
7
6
5
4
3
2
1
0
Bit Name

EP3 PKTE
EP1 RDFN
EP2 PKTE

EP0s RDFN
EP0o RDFN
EP0i PKTE
Bit Name
Bit Name
USB Function Controller (USBF)
Initial Value R/W
All 0
Initial Value R/W
All 0
0
0
Initial Value R/W Description
0
0
0
0
0
0
R
R
W
W
W
W
W
W
W
W
Description
Number of received bytes for endpoint 1
Description
Number of received bytes for endpoint 4
Reserved
Reserved
EP0s Read Complete
EP0o Read Complete
EP0i Packet Enable
The write value should always be 0.
EP3 Packet Enable
EP1 Read Complete
EP2 Packet Enable
The write value should always be 0.