HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 281

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.1.2
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Note: Initialized to H'000 at power-on reset and H'020 at manual reset.
7.1.3
INTEVT is assigned to address H'FFFFFFD8 and stores an exception code or a code which
indicates interrupt priority order. A code to be specified when an interrupt occurs is determined by
an interrupt source. (For details, see section 8.4.6, Interrupt Exception Handling and Priority.)
These exception and interrupt priority order codes are automatically specified by the hardware
when an exception occurs. INTEVT can be modified using the software. Only bits 11 to 0 of
INTEVT can be modified using the software.
Bit
31 to 12
11 to 0
Bit
31 to 12
11 to 0
Exception Event Register (EXPEVT)
Interrupt Event Register (INTEVT)
Bit Name

EXPEVT
Bit Name

INTEVT
Initial
Value
All 0
*
Initial
Value
All 0

R/W
R
R/W
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Rev. 3.00 Jan. 18, 2008 Page 219 of 1458
Section 7 Exception Handling
REJ09B0033-0300