HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1176

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 33 User Break Controller (UBC)
33.2.2
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
33.2.3
BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)
instruction fetch or data access, (3) read or write, and (4) operand size as the break conditions of
channel A.
Rev. 3.00 Jan. 18, 2008 Page 1114 of 1458
REJ09B0033-0300
Bit
31 to 0 BAMA31 to
Bit
15 to 8 
7
6
Bit Name
BAMA 0
Bit Name
CDA1
CDA0
Break Address Mask Register A (BAMRA)
Break Bus Cycle Register A (BBRA)
Initial
Value
All 0
Initial
Value
All 0
0
0
R/W
R/W
R/W
R
R/W
R/W
Description
Break Address Mask A
Specify bits masked in the channel A break address bits
specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
1: Break address bit BAAn of channel A is masked and
Note: n = 31 to 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
L Bus Cycle/I Bus Cycle Select A
Select the L bus cycle or I bus cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
the break condition
is not included in the break condition