HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 683

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(5)
Figures 18.7 and 18.8 show sample serial reception flowcharts. After SCIF reception is enabled,
use the following procedure to perform serial data reception.
Transmitting and Receiving Data (Serial data reception)
No
No
Read receive data in SCFRDR,
Clear RE bit in SCSCR to 0
Read RDF flag in SCSSR
Figure 18.7
and clear RDF flag in
Read PER and FER
All data received?
PER or FER = 1?
Start reception
flags in SCSSR
End reception
SCSSR to 0
RDF = 1?
No
Yes
Yes
Sample Serial Reception Flowchart (1)
Error processing
Section 18
Yes
(1)
(2)
(3)
(1) Receive error handling and break
(2) SCIF status check and receive data
(3) Serial reception continuation
detection:
Read the DR, ER, and BRK flags in
SCSSR2 to identify any error, perform
the appropriate error handling, then
clear the DR, ER, and BRK flags to 0.
In the case of a framing error, a break
can also be detected by reading the
value of the RxD2 pin.
read :
Read the serial status register
(SCSSR) and check that RDF = 1, then
read the receive data in the receive
FIFO data register (SCFRDR), read 1
from the RDF flag, and then clear the
RDF flag to 0.
procedure:
To continue serial reception, read at
least the receive trigger set number of
receive data bytes from SCFRDR, read
1 from the RDF flag, then clear the
RDF flag to 0. The number of receive
data bytes in SCFRDR can be
ascertained by reading the lower bits of
SCFDR.
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 621 of 1458
REJ09B0033-0300