HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1099

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

31.3.5
TBNCR sets the number of blocks to be transferred when multiblock transfer is specified by bits
TY5 and TY6 in CMDTYR. The contents of TBNCR is decremented for every 1-block transfer
completion. When the contents of TBNCR is 0, the command sequence is terminated, and an
interrupt is generated.
31.3.6
CMDR are six 8-bit registers. A command is written to CMDR as shown in table 31.3, and a
command is transmitted by setting the START bit in CMDSTRT to 1.
Table 31.3 CMDR Configuration
• CMDR0
Bit
15 to 0 TBNCR
Register
CMDR0
CMDR1 to CMDR4
CMDR5
Bit
7
6
5 to 0
Bit Name
Bit Name
Start
Host
INDEX
Transfer Block Number Counter (TBNCR)
Command Registers 0 to 5 (CMDR0 to CMDR5)
Initial
Value
0
0
All 0
Initial
Value
All 0
Contents
Start bit, Host bit, and
command index
Command argument
CRC, End bit
R/W
R/W
R/W
R/W
R/W
R/W
Description
Start bit (This bit should be set to 0)
Transmission bit (This bit should be set to 1)
Command indexes
Description
Transfer Block Number Counter
[Clearing condition]
When the specified number of blocks are transferred and
0 is written to TBNCR.
Operation
Command index writing
Sets the Start bit to 0, and the Host bit to 1.
Command argument writing
Setting of CRC is unnecessary (automatic
calculation)
Setting of end bit is unnecessary (end bit is set to 1)
Section 31
Rev. 3.00 Jan. 18, 2008 Page 1037 of 1458
MultiMediaCard Interface (MMCIF)
REJ09B0033-0300