DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 111
DF2170BVTE33V
Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170BVTE33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 5.6 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt request is sent to the interrupt controller.
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
when the I bit is set to 1 while the UI bit is cleared to 0.
An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0.
When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other
interrupts are held pending.
When both the I and UI bits are set to 1, only an NMI or address break interrupt request is
accepted, and other interrupts are held pending.
When the I bit is cleared to 0, the UI bit is not affected.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
break interrupt.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 2.00, 03/04, page 77 of 534
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