DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 393

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.7
12.7.1
If the USB continues to be idle for the specified time, the USB enters the suspend state. When the
USB enters the suspend state, the USSUSP signal is asserted to low and the suspend state can be
notified to the external transceiver.
When the external transceiver receives the USSUSP signal, the clock oscillation is stopped and the
power-down state is entered. Therefore the USCLK supplied to this LSI is stopped. To operate the
USB module, the USCLK supplied by the external transceiver and system clock (φ) should be
supplied. While the USCLK is stopped, programming is required so that access to the USB
module does not occur.
In this example, when the first 512 bytes of data has not been transmitted to the host at the end
of DMA transfer on the first 512 bytes of data and second 512 bytes of data, the DMA request
does not occur. If the transmission has been completed, the DMA request occurs because there
is space in the one FIFO.
When the last 26 bytes of data has been transferred, there is no data to be transferred in the
firmware. However, the DMA request occurs if there is space in the FIFO. Therefore, when
DMA transfer is completed on all data, the DMA enable state should be cleared by writing 0 to
the EP2DMAE bit in DMA0. Note that over-sampling should not be performed by the DMAC.
Generally the number of transmit data is set as the number of DMAC transfers and the number
of data less than the maximum packet size is written in PKTE2 using the DMA transfer end
interrupt. If the number of transmit data is an integral multiple of the maximum packet size
(for example, 1024 bytes or 2048 bytes), the number of transmit data is automatically written
in PKTE2. In this case, the user must not write the number of transmit data in PKTE2 using the
DMA transfer end interrupt. If the writing is performed, correct operation cannot be
guaranteed.
Suspend Signal Output
Transition to USB Suspend Mode
512 bytes
Figure 12.15 PKTE2 Operation for EP2
PKTE2
(Automatically
performed)
512 bytes
PKTE2
(Automatically
performed)
26 bytes
Executed by DMA transfer
end interrupt (user)
Rev. 2.00, 03/04, page 359 of 534
PKTE2 is
not performed

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