DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 187

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

This LSI has an on-chip DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
• Number of channels: Four channels
• Address space: Physical address space (16-Mbyte external space)
• Transfer data length: Byte, word, or longword can be selected.
• Maximum number of transfers: 16,777,215/infinite (free-running)
• Address mode: Dual address mode or single address mode can be selected.
• Transfer request: The DMAC transfer activation requests are as follows.
• Bus mode: Cycle steal mode or burst mode can be selected.
• Transfer mode: Normal mode or block transfer mode can be selected.
• Interrupt request: An interrupt request can be sent to the CPU at the end of the specified
EDMA261A_000120020400
Dual address mode
Addresses of transfer source and transfer destination are accessed.
Values set in the internal DMAC register are addresses to be accessed for transfer source and
transfer destination.
Single data transfer requires two bus cycles.
Single address mode
The peripheral device of transfer source or transfer destination is accessed by the DACK signal
and another one is accessed by the address. Single data transfer requires one bus cycle.
External request
Four DREQ pins. Low-level detection or falling-edge detection can be selected.
External requests can be accepted on all channels.
Auto request
A transfer request is automatically generated from the internal DMAC.
On-chip USB
A transfer request can be accepted from the on-chip USB on all channels.
Normal mode
Single data transfer is performed for single transfer request.
The number of transfers is specified as 24 bits (max. 16 Mbytes)
Block transfer mode (only for external request)
Single block (specified number) data transfer is performed for single transfer request.
number of transfers.
Features
Section 7 DMA Controller (DMAC)
Rev. 2.00, 03/04, page 153 of 534