DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 204

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Rev. 2.00, 03/04, page 170 of 534
Bit
12
11
10
9
8 to 0
Bit Name

EP2DMAE
UWCHS1
UWCHS0

Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit can be read from or written to. However, the
write value should always be 0.
Endpoint 2 (EP2) DMA Enable
Enables a transfer source from the on-chip USB
(transfer direction: writing to the on-chip USB). When
this bit is set to 1, a transfer request from the USB is
selected as a transfer source.
In block transfer mode, the on-chip USB request must
not be set as an activation source. While the DA bit in
DMMDR is set to 1, the EP2DMAE value must not be
changed.
0: Transfer request from on-chip USB (EP2) not
1: Transfer request from on-chip USB (EP2) accepted.
USB Write Channel Select
When the DMA transfer is performed by a transfer
request from the USB (EP2), these bits select the
DMAC channel to be used. When the channel which
accepts a request is selected and the EP2DMAE bit is
set to 1, the corresponding channel accepts a USB
request rather than an external request. In this case,
the transfer direction is writing to the on-chip USB
(EP2). Therefore, the destination address must be
specified as the FIFO in the on-chip USB (EP2).
While the DA bit in DMMDR is set to 1, these bits must
not be changed. A transfer request from the endpoint 1
(EP1) (reading from the on-chip USB) or a transfer
request from the endpoint 2 (EP2) (writing to the on-
chip USB) must not be set to the same channel.
00: Channel 0 can accept the EP2 transfer request.
01: Channel 1 can accept the EP2 transfer request.
10: Channel 2 can accept the EP2 transfer request.
11: Channel 3 can accept the EP2 transfer request.
Reserved
These bits can be read from or written to. However, the
write value should always be 0.
The DREQ pin on the corresponding channel is not
available.
accepted.