DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 210

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

7.4.3
Auto Request Mode: In auto request mode, transfer request signals are automatically generated
within the DMAC in cases where a transfer request signal is not issued from outside, such as in
transfer between two memories, or between a peripheral module that is not capable of generating
transfer requests and memory. In auto request mode, transfer is started when the DA bit is set to 1
in DMMDR.
In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.
Block transfer mode cannot be used.
External Request Mode: In external request mode, transfer is started by a transfer request signal
(DREQ) from a device external to this LSI. DMA transfer is started when DREQ is input while
DMA transfer is enabled (DA = 1).
The transfer request source need not be the data transfer source or data transfer destination.
The transfer request signal is accepted via the DREQ pin. Either falling edge sensing or low level
sensing can be selected for the DREQ pin by means of the DREQS bit in DMMDR (low level
sensing when DREQS = 0, falling edge sensing when DREQS = 1).
Setting the DRAKE bit to 1 in DMMDR enables a signal confirming transfer request acceptance
to be output from the DRAK pin. The DRAK signal is output when acceptance and transfer
processing has been started in response to a single external request. The DRAK signal enables the
external device to determine the timing of DREQ signal negation, and makes it possible to provide
handshaking between the transfer request source and the DMAC.
In external request mode, block transfer mode can be used instead of burst mode. Block transfer
mode allows continuous execution (burst operation) of the specified number of transfers (the block
size) in response to a single transfer request. In block transfer mode, the DRAK signal is output
only once for a one-block transfer, since the transfer request via the DREQ pin is for a block unit.
USB Request Mode: In USB request mode, DMA transfer can be executed by a transfer request
from the on-chip USB. When a transfer request from the USB can be accepted and DMA transfer
is enabled (DA = 1), DMA transfer is started after a transfer request from the USB is input.
When a transfer request for the endpoint 1 is accepted, the DMAC transfers the endpoint 1 data.
When a transfer request for the endpoint 2 is accepted, the DMAC transfers data to the endpoint 2.
When a transfer request from the USB is used as a transfer source, single address mode, block
transfer mode, and normal/burst transfer mode cannot be used.
Rev. 2.00, 03/04, page 176 of 534
DMA Transfer Requests (Auto Request Mode/External Request Mode/USB
Transfer Request)