DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 201

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit
7
6
5
Bit Name
DAT1
DAT0
DARIE
0
Initial
Value
0
0
R/W
R/W
R/W
R/W
Destination Address Update Mode
These bits specify incrementing/decrementing of the
transfer destination address (DMDAR). When an
external device with DACK is designated as the transfer
destination in single address mode, the specification by
these bits is ignored.
0X: Destination address (DMDAR) is fixed
10: Destination address is incremented (+1 in byte
11: Destination address is decremented (–1 in byte
Destination Address Repeat Interrupt Enable
Description
When this bit is set to 1, in the event of destination
address repeat area overflow the IRF bit is set to 1 and
the DA bit cleared to 0 in DMMDR, and transfer is
terminated. If the DIE bit in DMMDR is 1 when the IRF
bit in DMMDR is set to 1, an interrupt request is sent to
the CPU.
When used together with block transfer mode, a
destination address repeat interrupt is requested at the
end of a block-size transfer.
If the DA bit is set to 1 in DMMDR for the channel on
which transfer is terminated by a destination address
repeat interrupt, transfer can be resumed from the state
in which it ended.
If a destination address repeat area has not been
designated, this bit is ignored.
0: Destination address repeat interrupt is not requested
1: When destination address repeat area overflow
occurs, the IRF bit in DMMDR is set to 1 and an
interrupt is requested
transfer, +2 in word transfer, or +4 in longword
transfer)
transfer, –2 in word transfer, or –4 in longword
transfer)
Rev. 2.00, 03/04, page 167 of 534