DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 330

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Legend: X: Don't care
Rev. 2.00, 03/04, page 296 of 534
Bit
5
4
3
2
1
0
Bit Name
TE
RE
TEIE
CKE1
CKE0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Enable
When this bit s set to 1, transmission is enabled. In this
state, serial transmission is started when transmit data
is written to TDR and the TDRE flag in SSR is cleared
to 0. SMR setting must be performed to decide the
transfer format before setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission is
disabled by clearing this bit to 0.
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start bit is
detected in asynchronous mode. SMR setting must be
performed to decide the transfer format before setting
the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF, FER,
PER, and ORER flags, which retain their states.
Reserved
The initial value should not be changed.
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled. TEI cancellation can be performed by reading
1 from the TDRE flag in SSR, then clearing it to 0 and
clearing the TEND flag to 0, or by clearing the TEIE bit
to 0.
Clock Enable 1 and 0
Selects the clock source.
Asynchronous mode
0X: On-chip baud rate generator
1X: Setting prohibited

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