DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 248

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Interrupt sources can be enabled or disabled by means of the DIE bit in DMMDR for the relevant
channel, and can be sent to the interrupt controller independently.
The relative priority of the channels is determined by the interrupt controller (see table 7.4). Figure
7.46 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever the DIE
bit is set to 1 while the IRF bit is set to 1 in DMMDR.
Interrupt source settings are made individually with the interrupt enable bits in the registers for the
relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of
the TCEIE bit in DMMDR, the source address register repeat area overflow interrupt by means of
the SARIE bit in DMACR, and the destination address register repeat area overflow interrupt by
means of the DARIE bit in DMACR. When an interrupt source occurs while the corresponding
interrupt enable bit is set to 1, the IRF bit in DMMDR is set to 1. The IRF bit is set by all interrupt
sources indiscriminately.
The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in DMMDR within the
interrupt handling routine, or by re-setting the transfer counter and address registers and then
setting the DA bit to 1 in DMMDR to perform transfer continuation processing.
An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown
in figure 7.47.
Rev. 2.00, 03/04, page 214 of 534
IRF bit
DIE bit
Figure 7.46 Transfer End Interrupt Logic
Transfer end interrupt