DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 23

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Arrangement (TFP-100B) ....................................................................................... 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 17
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 17
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 18
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 19
Figure 2.5 Memory Map............................................................................................................... 20
Figure 2.6 CPU Internal Registers ................................................................................................ 21
Figure 2.7 Usage of General Registers ......................................................................................... 22
Figure 2.8 Stack............................................................................................................................ 23
Figure 2.9 General Register Data Formats (1).............................................................................. 26
Figure 2.9 General Register Data Formats (2).............................................................................. 27
Figure 2.10 Memory Data Formats............................................................................................... 28
Figure 2.11 Instruction Formats (Examples) ................................................................................ 40
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ...................... 43
Figure 2.13 State Transitions ........................................................................................................ 47
Section 3 MCU Operating Modes
Figure 3.1 Address Map ............................................................................................................... 53
Section 4 Exception Handling
Figure 4.1 Reset Sequence............................................................................................................ 58
Figure 4.2 Stack Status after Exception Handling ........................................................................ 60
Figure 4.3 Operation when SP Value is Odd................................................................................ 61
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 63
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 ................................................................ 69
Figure 5.3 Block Diagram of Interrupt Control Operation ........................................................... 72
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 75
Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 76
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 78
Figure 5.7 Interrupt Exception Handling ...................................................................................... 79
Figure 5.8 Conflict between Interrupt Generation and Disabling................................................. 81
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller................................................................................ 84
Figure 6.2 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)..................................................... 89
Rev. 2.00, 03/04, page xxi of xxxii