DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 127

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.3.5
RDNCR selects the read strobe signal (RD) negation timing in a read access to normal space.
Bit
7
6
5
4
3 to 0
RDNn = 0
RDNn = 1
Legend
n = 3 to 0
Figure 6.3 Read Strobe Negation Timing (Example of 3-State Access Space)
Bit Name
RDN3
RDN2
RDN1
RDN0

Read Strobe Timing Control Register (RDNCR)
Data
Data
Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
T
1
Description
Reserved
Read Strobe Timing Control 3 to 0
These bits set the negation timing of the read strobe in
a corresponding area read access.
As shown in figure 6.3, the read strobe for an area for
which the RDNn bit is set to 1 is negated one half-state
earlier than that for an area for which the RDNn bit is
cleared to 0. The read data setup and hold time
specifications are also one half-state earlier.
0: In an area n read access, the RD is negated at the
1: In an area n read access, the RD is negated one
These bits can be read from or written to. However, the
write value should always be 0.
end of the read cycle
half-state before the end of the read cycle
Bus cycle
T
2
Rev. 2.00, 03/04, page 93 of 534
T
3
(n = 3 to 0)