DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 141

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
Chip Select (CS) Assertion Period Extension States: Some external I/O devices require a setup
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
6.4.4
Memory Interfaces
The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; and a DRAM interface that allows direct connection of DRAM. The
interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space and an area for
which the DRAM interface is designated functions as DRAM space
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is 8
bits.
Area 0: Area 0 includes on-chip ROM and the space excluding on-chip ROM is external address
space by setting the EXPE bit in MDCR to 1.
When area 0 external space is accessed, the CS0 signal can be output.
Only basic bus interface can be used for area 0.
Area 1: All of area 1 is external address space by setting the EXPE bit in MDCR to 1.
When area 1 external address space is accessed, the CS1 signal can be output.
Only basic bus interface can be used for area 1.
Area 2: All of area 2 is external address space by setting the EXPE bit in MDCR to 1.
When area 2 external space is accessed, signal CS2 can be output.
Basic bus interface or DRAM interface can be selected for area 2. With the DRAM interface, the
CS2 signal is used as the RAS signal.
If area 2 is designated as DRAM space, large-capacity (e.g. 64-Mbit) DRAM can be connected. In
this case, the CS2 signal is used as the RAS signal for DRAM space.
Rev. 2.00, 03/04, page 107 of 534