DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 203

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.3.6
USTCR specifies the transfer source from the on-chip USB, etc.
Bit
15
14
13
Bit Name
EP1DMAE
URCHS1
URCHS0
USB Transfer Control Register (USTCR)
0
Initial
Value
0
0
R/W
R/W
R/W
R/W
Endpoint 1 (EP1) DMA Enable
Description
Enables a transfer source from the on-chip USB
(transfer direction: reading from the on-chip USB
(EP1)). When this bit is set to 1, a transfer request from
the USB is selected as a transfer source.
In block transfer mode, the on-chip USB request must
not be set as an activation source. While the DA bit in
DMMDR is set to 1, the EP1DMAE value must not be
changed.
0: Transfer request from on-chip USB (EP1) not
1: Transfer request from on-chip USB (EP1) accepted.
USB Read Channel Select
When the DMA transfer is performed by a transfer
request from the USB (EP1), these bits select the
DMAC channel to be used. When the channel which
accepts a request is selected and the EP1DMAE bit is
set to 1, the corresponding channel accepts a USB
request rather than an external request. In this case,
the transfer direction is reading from the USB (EP1).
Therefore, the source address must be specified as the
FIFO in the USB (EP1).
While the DA bit in DMMDR is set to 1, these bits must
not be changed. A transfer request from the endpoint 1
(EP1) (reading from the on-chip USB) or a transfer
request from the endpoint 2 (EP2) (writing to the on-
chip USB) must not be set to the same channel.
00: Channel 0 can accept the EP1 transfer request.
01: Channel 1 can accept the EP1 transfer request.
10: Channel 2 can accept the EP1 transfer request.
11: Channel 3 can accept the EP1 transfer request.
The DREQ pin on the corresponding channel is not
available.
accepted.
Rev. 2.00, 03/04, page 169 of 534

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